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| Z86C61/62/96 Z8(R) MICROCONTROLLER PRODUCT SPECIFICATION Z86C61/62/96 CMOS Z8(R) MICROCONTROLLER FEATURES s s 8-Bit CMOS Microcontroller 40-Pin DIP, 44-Pin PLCC, 64-Pin DIP, or 68-Pin PLCC Package 32 Input/Output Lines (Z86C61 Only) s s s Auto Latches RAM and ROM Protect 16 Kbytes of ROM 256 Bytes of RAM Two Programmable 8-Bit Counter/Timers, Each with 6-Bit Programmable Prescaler Six Vectored, Priority Interrupts from Eight Different Sources Clock Speeds: 16 and 20 MHz On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, or External Clock Drive s s s s s s s s s 52 Input/Output Lines (Z86C62 and Z86C96) s 3.0V to 5.5V Operating Range Low Power Consumption: 200 mW (max) Fast Instruction Pointer: 0.75 s @ 16 MHz s s Two Standby Modes: STOP and HALT s Full-Duplex UART All Digital Inputs are TTL Levels GENERAL DESCRIPTION The Z86C61/62/96 microcontroller is a member of the Z8 single-chip microcontroller family with 16 Kbytes of ROM and 256 bytes of RAM. The Z86C96 is ROMless. The Z86C61 is offered in 40-pin DIP and 44-pin PLCC style packages, however, the ROMless pin option is available on the 44-pin version only. The Z86C62/96 is offered in 64pin DIP and 68-pin PLCC style packages. A ROMless pin option enables these MCUs to address both external memory and preprogrammed ROM, making them wellsuited for high-volume applications or where code flexibility is required. With 16 Kbytes of ROM and 256 bytes of general-purpose RAM, these low-cost, low power consumption CMOS Z86C61/62/96 MCUs offer fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion. The Z86C61/62/96 architecture is characterized by Zilog's 8-bit microcontroller core. The device offers a flexible I/O scheme, an efficient register and address space structure, multiplexed capabilities between address/data, I/O, and a number of ancillary features that are useful in many industrial and advanced scientific applications. For applications which demand powerful I/O capabilities, the Z86C61 fulfills this with 32 pins dedicated to input and output. These lines are grouped into four ports with eight lines each. The Z86C62/96 has 52 pins for input and output, and these lines are grouped into six, 8-bit ports and one 4-bit port. Each port is configurable under software control to provide timing, status signals, serial or parallel I/O with or without handshake, and an address/data bus for interfacing external memory. 1 Z86C61/62/96 Z8(R) MICROCONTROLLER GENERAL DESCRIPTION (Continued) There are three basic address spaces available to support this configuration: Program Memory, Data Memory, and 236 General-Purpose Registers. To unburden the program from coping with the real-time tasks, such as counting/timing and serial data communication, the Z86C61/62/96 offers two on-chip counter/timers with a large number of user selectable modes, and an on-board UART (Figures 1, 2, and 3). Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS Output Input Vcc GND XTAL /AS /DS R//W /RESET Port 3 Machine Timing and Instruction Control UART ALU Counter/ Timers (2) FLAGS Prg. Memory 16,384 x 8-Bit Interrupt Control Register Pointer Register File 256 x 8-Bit Program Counter Port 2 Port 0 Port 1 4 I/O (Bit Programmable) 4 8 Address/Data or I/O (Byte Programmable) Address or I/O (Nibble Programmable) Figure 1. Z86C61 Functional Block Diagram 2 Z86C61/62/96 Z8(R) MICROCONTROLLER Output Input Vcc GND XTAL /AS /DS R//W /RESET Port 3 Machine Timing and Instruction Control UART ALU Flags Counter/ Timers (2) Register Pointer Interrupt Control Register File 256 x 8-Bit Program Memory 16,384 x 8-Bit Program Counter Port 6 Port 5 Port 4 Port 2 4 I/O (Bit Programmable) Port 0 4 Port 1 8 Address/Data or I/O (Byte Programmable) I/O (Bit Programmable) Address or I/O (Nibble Programmable) Figure 2. Z86C62 Functional Block Diagram 3 Z86C61/62/96 Z8(R) MICROCONTROLLER GENERAL DESCRIPTION (Continued) Output Input Vcc GND XTAL /AS /DS R//W /RESET Port 3 Machine Timing and Instruction Control UART ALU Flags Counter/ Timers (2) Register Pointer Interrupt Control Register File 256 x 8-Bit Program Counter Port 6 Port 5 Port 4 Port 2 4 Port 0 4 Port 1 8 Address/Data or I/O (Byte Programmable) I/O (Bit Programmable) Address or I/O (Nibble Programmable) Z-BUS When Used As Address/Data Bus Figure 3. Z86C96 Functional Block Diagram 4 Z86C61/62/96 Z8(R) MICROCONTROLLER PIN DESCRIPTION Table 1. Z86C61 40-Pin DIP Pin Identification VCC XTAL2 XTAL1 P37 P30 /RESET R//W /DS /AS P35 GND P32 P00 P01 P02 P03 P04 P05 P06 P07 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P36 P31 P27 P26 P25 P24 P23 P22 P21 P20 P33 P34 P17 P16 P15 P14 P13 P12 P11 P10 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13-20 21-28 29 30 31-38 39 40 Symbol VCC XTAL2 XTAL1 P37 P30 /RESET R//W /DS /AS P35 GND P32 P07-P00 P17-P10 P34 P33 P27-P20 P31 P36 Function Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Reset Read/Write Data Strobe Address Strobe Port 3, Pin 5 Direction Input Output Input Output Input Input Output Output Output Output Z86C61 11 DIP 12 13 14 15 16 17 18 19 20 Ground Input Port 3, Pin 2 Input Port 0, Pins 0,1,2,3,4,5,6,7 In/Output Port 1, Pins 0,1,2,3,4,5,6,7 In/Output Port 3, Pin 4 Output Port 3, Pin 3 Input Port 2, Pins 0,1,2,3,4,5,6,7 In/Output Port 3, Pin 1 Input Port 3, Pin 6 Output Figure 4. Z86C61 40-Pin DIP Pin Assignments 5 Z86C61/62/96 Z8(R) MICROCONTROLLER PIN DESCRIPTION (Continued) XTAL1 XTAL2 VCC P30 P37 P36 P31 P27 P26 P25 N/C 6 /RESET R//W /DS /AS P35 GND P32 P00 P01 P02 R//RL 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 N/C P24 P23 P22 P21 P20 P33 P34 P17 P16 P15 Z86C61 PLCC 34 33 32 31 30 29 P03 P04 P05 P06 P07 P10 P12 P13 Figure 5. Z86C61 44-Pin PLCC Pin Assignments Table 2. Z86C61 44-Pin PLCC Pin Identification Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14-16 Symbol VCC XTAL2 XTAL1 P37 P30 N/C /RESET R//W /DS /AS P35 GND P32 P02-P00 Function Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Not Connected Reset Read/Write Data Strobe Address Strobe Port 3, Pin 5 Ground Port 3, Pin 2 Port 0, Pins 0,1,2 Direction Input Output Input Output Input Input Input Output Output Output Output Input Input In/Output Pin # 17 18-22 23-27 28 29-31 32 33 34-38 39 40-42 43 44 Symbol R//RL P07-P03 P14-P10 N/C P17-P15 P34 P33 P24-P20 N/C P25-P27 P31 P36 Function ROM/ROMless control Port 0, Pins 3,4,5,6,7 Port 1, Pins 0,1,2,3,4 Not Connected Port 1, Pins 5,6,7 Port 3, Pin 4 Port 3, Pin 3 Port 2, Pins 0,1,2,3,4 Not Connected Port 2, Pins 5,6,7 Port 3, Pin 1 Port 3, Pin 6 Direction Input In/Output In/Output Input In/Output Output Input In/Output Input In/Output Input Output 6 P14 P11 N/C Z86C61/62/96 Z8(R) MICROCONTROLLER Table 3. Z86C62 64-Pin DIP Pin Identification P44 VCC P45 XTAL2 XTAL1 P37 P30 N/C /RESET R//W /DS P46 P47 /AS P35 R//RL GND P32 P50 P51 P00 P01 P02 P03 P04 P05 P06 P07 VCC P52 P53 P54 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 P43 P42 P36 P31 P41 P40 P27 P26 P25 P24 P23 P22 P60 P61 P21 P20 GND P33 P34 P62 P63 P17 P16 P15 P14 P13 P12 P57 P56 P11 P10 P55 Pin # 1 2 3 4 5 6 7 8 9 10 11 12-13 14 15 16 17 18 19-20 21-28 29 30-33 34-35 36-37 38-43 44-45 46 47 48 49-50 51-52 53-58 59-60 61 62 63 64 Symbol P44 VCC P45 XTAL2 XTAL1 P37 P30 N/C /RESET R//W /DS P47-P46 /AS P35 R//RL GND P32 P51-P50 P07-P00 VCC P52-P55 P11-P10 P57-P56 P17-P12 P63-P62 P34 P33 GND P21-P20 P61-P60 P27-P22 P41-P40 P31 P36 P42 P43 Function Port 4, Pin 4 Power Supply Port 4, Pin 5 Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Not Connected Reset Read/Write Data Strobe Port 4, Pin 6,7 Address Strobe Port 3, Pin 5 ROM/ROMless control Ground Port 3, Pin 2 Port 5, Pin 0,1 Port 0, Pins 0,1,2,3,4,5,6,7 Power Supply Port 5, Pins 2,3,4,5 Port 1, Pins 0,1 Port 5, Pins 6,7 Port 1, Pins 2,3,4,5,6,7 Port 6, Pins 3,2 Port 3, Pin 4 Port 3, Pin 3 Ground Port 2, Pins 0,1 Port 6, Pins 1,0 Port 2, Pins 2,3,4,5,6,7 Port 4, Pins 0,1 Port 3, Pin 1 Port 3, Pin 6 Port 4, Pin 2 Port 4, Pin 3 Direction In/Output Input In/Output Output Input Output Input Input Input Output Output In/Output Output Output Input Input Input In/Output In/Output Input In/Output In/Output In/Output In/Output In/Output Output Input Input In/Output In/Output In/Output In/Output Input Output In/Output In/Output Z86C62 DIP 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Figure 6. Z86C62 64-Pin DIP Pin Assignments 7 Z86C61/62/96 Z8(R) MICROCONTROLLER PIN DESCRIPTION (Continued) es et P3 0 P3 7 XT AL 1 XT AL P4 2 5 VC C P4 4 P4 3 P4 2 P3 6 P3 1 P4 1 P4 0 P2 7 P2 6 P2 5 /R 9 R//W /P0DS /DS P46 P47 /P1DS /AS /DTimers P35 R//RL GND P32 P50 P51 P00 P01 P02 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 P24 P23 P22 P60 P61 P21 P20 SCLK /SYNC GND P33 P34 P62 P63 P17 P16 P15 Z86C62 PLCC 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 5 P0 6 P0 7 VC C P5 2 3 P5 4 P5 5 P1 0 P1 1 P5 6 3 4 7 P1 2 P1 3 4 P1 P0 P0 P5 Figure 7. Z86C62 68-Pin PLCC Pin Assignments 8 P0 P5 Z86C61/62/96 Z8(R) MICROCONTROLLER Table 4. Z86C62 68-Pin PLCC Pin Identification Pin # 1-2 3 4 5 6 7 8 9 10 11 12 13-14 15 16 17 18 19 20 21 22-23 Symbol P44-P43 VCC P45 XTAL2 XTAL1 P37 P30 /RESET R//W /P0DS Function Port 4, Pins 3,4 Power Supply Port 4, Pin 5 Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Reset Read/Write Port 0 Data Strobe Direction In/Output Input In/Output Output Input Output Input Input Output Output Output In/Output Output Output Input Output Input Input Input In/Output Pin # 24-31 32 33-36 37-38 39-40 41-46 47-48 49 50 51 52 53 54-55 56-57 58-63 64-65 66 67 68 Symbol P07-P00 VCC P55-P52 P11-P10 P56-P57 P17-P12 P63-P62 P34 P33 GND /SYNC SCLK P21-P20 P60-P61 P27-P22 P41-P40 P31 P36 P42 Function Direction Port 0, Pins 0,1,2,3,4,5,6,7 In/Output Power Supply Input Port 5, Pins 2,3,4,5 In/Output Port 1, Pins 0,1 In/Output Port 5, Pins 6,7 Port 1, Pins 2,3,4,5,6,7 Port 6, Pins 3,2 Port 3, Pin 4 Port 3, Pin 3 Ground Synchronization System Clock Port 2, Pins 0,1 Port 6, Pins 1,0 Port 2, Pins 2,3,4,5,6,7 Port 4, Pins 0,1 Port 3, Pin 1 Port 3, Pin 6 Port 4, Pin 2 In/Output In/Output In/Output Output Input Input Output Output In/Output In/Output In/Output In/Output Input Output In/Output /DS Data Strobe P47-P46 Port 4, Pins 6,7 /P1DS Port 1, Data Strobe /AS Address Strobe /DTIMER DTIMER P35 R//RL GND P32 P51-P50 Port 3, Pin 5 ROM/ROMless control Ground Port 3, Pin 2 Port 5, Pins 0,1 9 Z86C61/62/96 Z8(R) MICROCONTROLLER PIN DESCRIPTION (Continued) Table 5. Z86C96 64-Pin DIP Pin Identification P44 VCC P45 XTAL2 XTAL1 P37 P30 NC /RESET R//W /DS P46 P47 /AS P35 N/C GND P32 P50 P51 P00 P01 P02 P03 P04 P05 P06 P07 VCC P52 P53 P54 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 P43 P42 P36 P31 P41 P40 P27 P26 P25 P24 P23 P22 P60 P61 P21 P20 GND P33 P34 P62 P63 P17 P16 P15 P14 P13 P12 P57 P56 P11 P10 P55 Pin # Symbol 1 2 3 4 5 6 7 8 9 10 11 12-13 14 15 16 17 18 19-20 21-28 29 30-33 34-35 36-37 38-43 44-45 46 47 48 49-50 51-52 53-58 59-60 61 62 63 64 P44 VCC P45 XTAL2 XTAL1 P37 P30 N/C /RESET R//W /DS P47-P46 /AS P35 N/C GND P32 P51-P50 P07-P00 VCC P55-P52 P11-P10 P56-P57 P17-P12 P63-P62 P34 P33 GND P21-P20 P61-P60 P27-P22 P41-P40 P31 P36 P42 P43 Function Port 4, Pin 4 Power Supply Port 4, Pin 5 Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Not Connected Reset Read/Write Data Strobe Port 4, Pins 6,7 Address Strobe Port 3, Pin 5 Not Connected Ground Port 3, Pin 2 Port 5, Pins 0,1 Port 0, Pins 0,1,2,3,4,5,6,7 Power Supply Port 5, Pins 2,3,4,5 Port 1, Pins 0,1 Port 5, Pins 6,7 Port 1, Pins 2,3,4,5,6,7 Port 6, Pins 3,2 Port 3, Pin 4 Port 3, Pin 3 Ground Port 2, Pins 0,1 Port 6, Pins 1,0 Port 2, Pins 2,3,4,5,6,7 Port 4, Pins 0,1 Port 3, Pin 1 Port 3, Pin 6 Port 4, Pin 2 Port 4, Pin 3 Direction In/Output Input In/Output Output Input Output Input Input Input Output Output In/Output Output Output Input Input Input In/Output In/Output Input In/Output In/Output In/Output In/Output In/Output Output Input Input In/Output In/Output In/Output In/Output Input Output In/Output In/Output Z86C96 DIP 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Figure 8. Z86C96 64-Pin DIP Pin Assignments 10 Z86C61/62/96 Z8(R) MICROCONTROLLER SE P3 T 0 P3 7 XT AL 1 XT AL P4 2 5 VC C P4 4 P4 3 P4 2 /R E 9 R//W /P0DS /DS P46 P47 /P1DS /AS /DTimers P35 N/C GND P32 P50 P51 P00 P01 P02 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 P24 P23 P22 P60 P61 P21 P20 SCLK /SYNC GND P33 P34 P62 P63 P17 P16 P15 P3 6 P3 1 P4 1 P4 0 P2 7 Z86C96 PLCC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 3 6 P0 7 VC C P5 2 P5 3 P5 4 P5 5 P1 0 P1 1 6 P5 7 P1 2 3 4 5 P1 P0 P0 P0 Figure 9. Z86C96 68-Pin PLCC Pin Assignments P0 P5 P1 4 P2 6 P2 5 53 52 51 50 49 48 47 46 45 44 11 Z86C61/62/96 Z8(R) MICROCONTROLLER PIN DESCRIPTION (Continued) Table 6. Z86C96 68-Pin PLCC Pin Identification Pin # 1-2 3 4 5 6 7 8 9 10 11 12 13-14 15 16 17 18 19 20 21 22-23 Symbol P44-P43 VCC P45 XTAL2 XTAL1 P37 P30 /RESET R//W /P0DS Function Port 4, Pins 3,4 Power Supply Port 4, Pin 5 Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Reset Read/Write Port 0 Data Strobe Direction In/Output Input In/Output Output Input Output Input Input Output Output Output In/Output Output Output Input Output Input Input Input In/Output Pin # 24-31 32 33-36 37-38 39-40 41-46 47-48 49 50 51 52 53 54-55 56-57 58-63 64-65 66 67 68 Symbol P07-P00 VCC P55-P52 P11-P10 P57-P56 P17-P12 P63-P62 P34 P33 GND /SYNC SCLK P21-P20 P61-P60 P27-P22 P41-P40 P31 P36 P42 Function Port 0, Pins 0,1,2,3,4,5,6,7 Power Supply Port 5, Pins 2,3,4,5 Port 1, Pins 0,1 Port 5, Pins 6,7 Port 1, Pins 2,3,4,5,6,7 Port 6, Pins 3,2 Port 3, Pin 4 Port 3, Pin 3 Ground Synchronization System Clock Port 2, Pins 0,1 Port 6, Pins1,0 Port 2, Pins 2,3,4,5,6,7 Port 4, Pins 0,1 Port 3, Pin 1 Port 3, Pin 6 Port 4, Pin 2 Direction In/Output Input In/Output In/Output In/Output In/Output In/Output Output Input Input Output Output In/Output In/Output In/Output In/Output Input Output In/Output /DS Data Strobe P47-P46 Port 4, Pins 6,7 /P1DS Port 1 Data Strobe /AS Address Strobe /DTIMER Disable Timers P35 N/C GND P32 P51-P50 Port 3, Pin 5 Not Connected Ground Port 3, Pin 2 Port 5, Pins 0,1 PIN FUNCTIONS R//RL (input, active Low). This pin when connected to GND disables the internal ROM and forces the device to function as a Z86C96 ROMless Z8. (Note: When left unconnected or pulled High to VCC the part functions as a normal Z86C61/62 ROM version.) This pin is only available on the 44-pin version of the Z86C61, and both versions of the Z86C62. /DS (output, active Low). Data Strobe is activated once for each external memory transfer. For a READ operation, data must be available prior to the trailing edge of /DS. For WRITE operations, the falling edge of /DS indicates that output data is valid. /AS (output, active Low). Address Strobe is pulsed once at the beginning of each machine cycle. Address output is through Port 1 for all external programs. Memory address transfers are valid at the trailing edge of /AS. Under program control, /AS can be placed in the highimpedance state along with Ports 0 and 1, Data Strobe, and Read/Write. XTAL1, XTAL2 Crystal 1, Crystal 2 (time-based input and output, respectively). These pins connect a parallelresonant crystal, ceramic resonator, LC, or any external single-phase clock to the on-chip oscillator and buffer. R//W (output, write Low). The Read/Write signal is Low when the MCU is writing to the external program or data memory. /RESET (input, active Low). To avoid asynchronous and noisy reset problems, the Z86C61/62/96 is equipped with a reset filter of four external clocks (4TpC). If the external /RESET signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the /RESET is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external /RESET, whichever is longer. During the reset cycle, /DS is held active Low while /AS cycles at a rate of TpC/2. When /RESET is deactivated, program execution begins at location 000C (HEX). Reset time must be held Low for 50 ms, or until VCC is stable, whichever is longer. 12 Z86C61/62/96 Z8(R) MICROCONTROLLER /P0DS Port 0 Data Strobe (output, active Low). Signal used to emulate Port 0 when in ROMless mode. /P1DS Port 1 Data Strobe (output, active Low). Signal used to emulate Port 1 when in ROMless mode. /DTIMERS Disable Timers (input, active Low). All timers are stopped by the Low level at this pin. This pin has an internal pull up resistor. SCLK (output). System clock pin. /SYNC Instruction SYNC Signal (output, active Low). This signal indicates the last clock of the current executing instruction. Port 0 (P07-P00). Port 0 is an 8-bit, nibble programmable, bidirectional, TTL compatible port. These eight I/O lines can be configured under software control as a nibble I/O port, or as an address port for interfacing external memory. When used as an I/O port, Port 0 may be placed under handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control /DAV0 and RDY0 (Data Available and Ready). Handshake signal assignment is dictated by the I/O direction of the upper nibble P07-P04. The lower nibble must have the same direction as the upper nibble to be under handshake control. For external memory references, Port 0 can provide address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 Mode register. In ROMless mode, after a hardware reset, Port 0 lines are defined as address lines A15-A8, and extended timing is set to accommodate slow memory access. The initialization routine includes reconfiguration to eliminate this extended timing mode (Figure 10). 4 Port 0 (I/O) MCU 4 Handshake Controls /DAV0 and RDY0 (P32 and P35) OEN PAD Out TTL Level Shifter In Auto Latch R 500 K Figure 10. Port 0 Configuration 13 Z86C61/62/96 Z8(R) MICROCONTROLLER PIN FUNCTIONS (Continued) Port 1 (P17-P10). Port 1 is an 8-bit, byte programmable, bidirectional, TTL compatible port. It has multiplexed Address (A7-A0) and Data (D7-D0) ports. For Z86C61/62/96, these eight I/O lines can be programmed as Input or Output lines or can be configured under software control as an address/data port for interfacing external memory. When used as an I/O port, Port 1 may be placed under handshake control. In this configuration, Port 3 line P33 and P34 are used as the handshake controls RDY1 and /DAV1. Memory locations greater than 16,384 are referenced through Port 1. To interface external memory, Port 1 must be programmed for the multiplexed Address/Data mode. If more than 256 external locations are required, Port 0 must output the additional lines. Port 1 can be placed in high-impedance state along with Port 0, /AS, /DS, and R//W, allowing the microcontroller to share common resources in multiprocessor and DMA applications. Data transfers can be controlled by assigning P33 as a Bus Acknowledge input, and P34 as a Bus request output (Figure 11). 8 MCU Port 1 (AD7-AD0) Handshake Controls /DAV1 and RDY1 (P33 and P34) OEN PAD Out TTL Level Shifter In Auto Latch R 500 K Figure 11. Port 1 Configuration 14 Z86C61/62/96 Z8(R) MICROCONTROLLER Port 2 (P27-P20). Port 2 is an 8-bit, bit programmable, bidirectional, CMOS compatible port. Each of these eight I/O lines can be independently programmed as an input or output or globally as an open-drain output. Port 2 is always available for I/O operation. When used as an I/O port, Port 2 may be placed under handshake control. In this configuration, Port 3 lines P31 and P36 are used as the handshake control lines /DAV2 and RDY2. The handshake signal assignment for Port 3 lines P31 and P36 is dictated by the direction (input or output) assigned to P27 (Figure 12). Port 2 (I/O) MCU Handshake Controls /DAV2 and RDY2 (P31 and P36) Open-Drain OEN PAD Out TTL Level Shifter In Auto Latch R 500 K Figure 12. Port 2 Configuration 15 Z86C61/62/96 Z8(R) MICROCONTROLLER PIN FUNCTIONS (Continued) Port 3 (P37-P30). Port 3 is an 8-bit, CMOS compatible fourfixed input and four-fixed output port. These eight I/O lines have four-fixed (P33-P30) input and four-fixed (P37P34) output ports. Port 3, when used as serial I/O, are programmed as serial in and serial out, respectively (Figure 13). MCU Port 3 (I/O or Control) PAD Out Port 3 Output Configuration PAD In Auto Latch R 500 K Port 3 Input Configuration Figure 13. Port 3 Configuration 16 Z86C61/62/96 Z8(R) MICROCONTROLLER Port 3 can be configured under software control to provide the following control functions: handshake for Ports 0 and 2 (/DAV and RDY); four external interrupt request signals (IRQ3-IRQ0); timer input and output signals (TIN and TOUT), and Data Memory Select (/DM). Table 7. Port 3 Pin Assignments Pin P30 P31 P32 P33 P34 P35 P36 P37 T0 T1 I/O IN IN IN IN OUT OUT OUT OUT CTC1 TIN Int. IRQ3 IRQ2 IRQ0 IRQ1 P0 HS P1 HS P2 HS D/R D/R D/R R/D R/D TOUT IRQ4 IRQ5 R/D Serial Out DM UART Serial In Ext Notes: HS = Handshake Signals D = Data Available R = Ready UART OPERATION Port 3 lines P30 and P37, can be programmed as serial I/O lines for full-duplex serial asynchronous receiver/ transmitter operation. The bit rate is controlled by the Counter/Timer0. The Z86C61/62/96 automatically adds a start bit and two stop bits to transmitted data (Figure 14). Odd parity is also available as an option. Eight data bits are always transmitted, regardless of parity selection. If parity is enabled, the eighth bit is the odd parity bit. An interrupt request (IRQ4) is generated on all transmitted characters. Received data must have a start bit, eight data bits and at least one stop bit. If parity is on, bit 7 of the received data is replaced by a parity error flag. Received characters generate the IRQ3 interrupt request. Note: UART function is only available in stardard timing mode (i.e., P01M D5 = 0). Transmitted Data (No Parity) SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST Start Bit Eight Data Bits Two Stop Bits Received Data (No Parity) SP D7 D6 D5 D4 D3 D2 D1 D0 ST Start Bit Eight Data Bits One Stop Bit Transmitted Data (With Parity) SP SP P D6 D5 D4 D3 D2 D1 D0 ST Start Bit Seven Data Bits Odd Parity Two Stop Bits Received Data (With Parity) SP P D6 D5 D4 D3 D2 D1 D0 ST Start Bit Seven Data Bits Parity Error Flag One Stop Bit Figure 14. Serial Data Formats 17 Z86C61/62/96 Z8(R) MICROCONTROLLER PIN FUNCTIONS (Continued) Port 4 (P47-P40). Port 4 is an 8-bit, bit programmable, bidirectional, CMOS compatible port. Each of these eight I/O lines can be independently programmed as an input or output or globally as an open-drain output. Port 4 is always available for I/O operation (Figure 15). Port address (F)02. Port 5 (P57-P50). Same as Port 4. Port address (F)04. Port 6 (P63-P60). Same as Port 4. (Note: this is a 4-bit port, bits D3-D0.) Port address (F)07. Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs that are not externally driven. This reduces excessive supply current flow in the input buffer when it is not being driven by any source. Port 4 (I/O) MCU Open-Drain OEN PAD Out TTL Level Shifter In Auto Latch R 500 K Figure 15. Port 4 Configuration 18 Z86C61/62/96 Z8(R) MICROCONTROLLER FUNCTIONAL DESCRIPTION Address Space Program Memory. The Z86C61/62 can address up to 48 Kbytes of external program memory (Figure 16). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. For ROM mode, byte 13 to byte 16383 consists of on-chip ROM. At addresses 16384 and greater, the Z86C61/62 executes external program memory fetches. The Z86C96, and the Z86C61/62 in ROMless mode, can address up to 64 Kbytes of external program memory. Program execution begins at external location 000CH after a reset. Data Memory (/DM). The ROM version can address up to 48 Kbytes of external data memory space beginning at location 16384. The ROMless version can address up to 64 Kbytes of external data memory. External data memory may be included with, or separated from, the external program memory space. /DM, an optional I/O function that can be programmed to appear on pin P34, is used to distinguish between data and program memory space (Figure 17). The state of the /DM signal is controlled by the type instruction being executed. An LDC opcode references PROGRAM (/DM inactive) memory, and an LDE instruction references DATA (/DM active Low) memory. 65535 65535 External ROM and RAM 16384 16383 On-Chip ROM Location of 12 First Byte of Instruction 11 Executed After RESET 10 9 8 Interrupt Vector (Lower Byte) 7 6 5 Interrupt Vector (Upper Byte) 4 3 2 1 0 IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 External Data Memory 16384 16383 Not Addressable IRQ1 IRQ1 IRQ0 IRQ0 0 Figure 17. Data Memory Configuration Figure 16. Program Memory Configuration 19 Z86C61/62/96 Z8(R) MICROCONTROLLER FUNCTIONAL DESCRIPTION (Continued) Register File. The Register File consists of four I/O port registers, 236 general-purpose registers and 16 control and status registers (Figure 18). There are eight further registers for I/O ports 4, 5 and 6 in the Expanded Register File (Bank F, R9-R2) (Figure 20). The instructions can access registers directly or indirectly through an 8-bit address field. The Z86C61/62/96 also allows short 4-bit register addressing using the Register Pointer (Figure 19). In the 4-bit mode, the Register File is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working-register group. Note: Register Bank E0-EF can only be accessed through working registers and indirect addressing modes. R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register Group Working Register Group Default Setting After Reset = 00000000 Figure 19. Register Pointer Register Location R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240 R239 General-Purpose Registers R4 R3 R2 R1 R0 Port 3 Port 2 Port 1 Port 0 Stack Pointer (Bits 7-0) Stack Pointer (Bits 15-8) Register Pointer Program Control Flags Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Ports 0-1 Mode Port 3 Mode Port 2 Mode T0 Prescaler Timer/Counter0 T1 Prescaler Timer/Counter1 Timer Mode Serial I/O Identifiers SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR SIO P3 P2 P1 P0 Figure 18. Register File 20 Z86C61/62/96 Z8(R) MICROCONTROLLER Z8 STANDARD CONTROL REGISTERS RESET CONDITION REGISTER % FF SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR SIO D7 D6 D5 D4 D3 D2 D1 D0 U U 0 U 0 0 U 0 0 1 U U U U 0 U U U 0 U U 0 U 1 0 1 U U U U 0 U U U 0 U U 0 U 0 0 1 U U U U 0 U U U 0 U U 0 U 0 0 1 U U U U 0 U U U 0 U U 0 U 1 0 1 U U U U 0 U U U 0 U U 0 U 1 0 1 U U U U 0 U U U 0 U U 0 U 0 0 1 U U 0 U 0 U U U 0 U U 0 U 1 0 1 0 U 0 U 0 U REGISTER POINTER 7 % FE 6 5 4 3 2 1 0 % FD Working Register Group Pointer Expanded Register Group Pointer % FC % FB % FA % F9 % F8 % F7 % F6 % F5 Z8 Reg. File %FF %F0 % F4 % F3 % F2 % F1 % F0 EXPANDED REG. GROUP (F) REGISTER % (F) 0F %7F % (F) 0E % (F) 0D % (F) 0C % (F) 0B % (F) 0A Reserved Reserved Reserved Reserved Reserved ICE P6M P6D P6 P45M P5D P5 P4D P4 Reserved Reserved U U U U U U U U U U U U U U U U U U U U 0 RESET CONDITION Reserved % (F) 09 % (F) 08 %0F %00 % (F) 07 % (F) 06 % (F) 05 % (F) 04 % (F) 03 % (F) 02 % (F) 01 % (F) 00 EXPANDED REG. GROUP (0) REGISTER % (0) 03 % (0) 02 % (0) 01 % (0) 00 U = Unknown = For Z86C96 (ROMless) Reset condition:"10110110" P3 P2 P1 P0 RESET CONDITION 1 U U U 1 U U U 1 U U U 1 U U U U U U U U U U U U U U U U U U U Figure 20. Expanded Register File Architecture 21 Z86C61/62/96 Z8(R) MICROCONTROLLER FUNCTIONAL DESCRIPTION (Continued) Expanded Register File. The register file has been expanded to allow for additional system control registers, and for mapping of additional peripheral devices along with I/O ports into the register address area. The Z8 register address space R0 through R15 has now been implemented as 16 groups of 16 registers per group. These register groups are known as the ERF (Expanded Register File). Bits 7-4 of Register RP select the working register group. Bits 3-0 of Register RP select the expanded register group (Figure 21). Eight I/O port registers reside in the Expanded Register File at Bank F. The rest of the Expanded Register is not physically implemented and is open for future expansion. The upper nibble of the register pointer (Figure 20) selects which group of 16 bytes in the register file, out of the full 256, will be accessed. The lower nibble selects the expanded register file bank and in the case of the Z86C61/ 62/96, only Bank F is implemented. A 0H in the lower nibble will allow the normal register file to be addressed, but any other value from 1H to FH will exchange the lower 16 registers in favor of an expanded register group of 16 registers. For example: Z86C61: (See Figures 18 and 19) R253 RP = 00H R0 = Port 0 R1 = Port 1 R2 = Port 2 R3 = Port 3 But If: R253 RP = 0FH R0 = Reserved R1 = Reserved R2 = Port 4 R3 = Port 4, Direction Register R9 = Port 6, Mode Register Further examples: SRP #0FH LD R2, #10010110 LD 2, #10010110 LD 9, #11110000 SRP #1FH LD R2, #11010110 LD 12H, #11010110 LD 2, #10010110 Set working group 0 and Bank F Load value into Port 4 using working register addressing. Load value into Port 4 using absolute addressing. Load value into Port 6 mode. Set working group 1 and Bank F Load value into general purpose register 12H Load value into general purpose register 12H Load value into Port 4 RAM Protect. The upper portion of the RAM's address spaces 80FH to EFH (excluding the control registers) can be protected from reading and writing. The RAM Protect bit option is mask-programmable and is selected by the customer when the ROM code is submitted. After the mask option is selected, the user can activate from the internal ROM code to turn off/on the RAM Protect by loading a bit D6 in the IMR register to either a 0 or a 1, respectively. A 1 in D6 indicates RAM Protect enabled. 22 Z86C61/62/96 Z8(R) MICROCONTROLLER ROM Protect. The first 16 Kbytes of program memory is mask programmable. A ROM protect feature prevents "dumping" of the ROM contents by inhibiting execution of LDC, LDCI, LDE, and LDEI instructions by external program memory when pointing to internal memory locations. Therefore these instructions can be used only when they are executed from internal memory, or if they are executed from external memory and pointing to external memory locations. The ROM Protect option is mask-programmable, to be selected by the customer at the time when the ROM code is submitted. Stack. The Z86C61/62/96 has a 16-bit Stack Pointer (R255R254) used for external stack that resides anywhere in the data memory for the ROMless mode, but only from 16384 to 65535 in the ROM mode. An 8-bit Stack Pointer (R255) is used for the internal stack that resides within the 236 general-purpose registers (R239-R4). The high byte of the Stack Pointer (SPH-Bit 8-15) can be used as a general purpose register when using internal stack only. Counter/Timers. There are two 8-bit programmable counter/timers (T0-T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler can be driven by internal or external clock sources; however, the T0 prescaler is driven by the internal clock only (Figure 22). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When both the counters and prescaler reach the end of the count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated. The counter can be programmed to start, stop, restart to continue, or restart from the initial value. The counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counter, but not the prescalers, can be read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and can be either the internal microprocessor clock divided-by-four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that can be retriggerable or nonretriggerable, or as a gate input for the internal clock. Port 3, line P36, also serves as a timer output (TOUT) through which T0, T1 or the internal clock can be output. The counter/timers can be cascaded by connecting the T0 output to the input of T1. r7 r6 r5 r4 r3 r2 r1 r0 R253 (Register Pointer) The upper nibble of the register file address provided by the register pointer specifies the active working-register group. FF Register Group F F0 EF 80 7F 70 6F 60 5F 50 4F 40 3F 30 2F 20 1F 10 0F Register Group 1 Register Group 0 I/O Ports * Expanded Register Group (0) is selected in this figure by handling bits D3 to D0 as "0" in Register R253 (RP). R15 to R0 R15 to R4* R3 to R0* Specified Working Register Group The lower nibble of the register file address provided by the instruction points to the specified register. 00 Figure 21. Register Pointer 23 Z86C61/62/96 Z8(R) MICROCONTROLLER FUNCTIONAL DESCRIPTION (Continued) Internal Data Bus Write OSC PRE0 Initial Value Register Write T0 Initial Value Register Read T0 Current Value Register /2 /4 Internal Clock 6-Bit Down Counter 8-bit Down Counter IRQ4 Serial I/O Clock /2 Tout P36 External Clock Clock Logic /4 6-Bit Down Counter 8-Bit Down Counter IRQ5 Internal Clock Gated Clock Triggered Clock PRE1 Initial Value Register Write Write T1 Initial Value Register Read T1 Current Value Register TIN P31 Internal Data Bus Figure 22. Counter/Timers Block Diagram 24 Z86C61/62/96 Z8(R) MICROCONTROLLER Interrupts. The Z86C61/62/96 has six different interrupts from eight different sources. The interrupts are maskable and prioritized. The eight sources are divided as follows: four sources are claimed by Port 3 lines P33-P30, one in Serial Out, one is Serial In, and two in the counter/timers (Figure 23). The Interrupt Mask Register globally or individually enables or disables the six interrupt requests. When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All Z86C61/62/96 interrupts are vectored through locations in the program memory. When an interrupt machine cycle is activated, an interrupt request is granted. Thus, this disables all of the subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request register is polled to determine which of the interrupt requests need service. Software initialed interrupts are supported by setting the appropriate bit in the Interrupt Request Register (IRQ). Internal interrupt requests are sampled on the falling edge of the last cycle of every instruction. The interrupt request must be valid 5TpC before the falling edge of the last clock cycle of the currently executing instruction. For the ROMless mode, when the device samples a valid interrupt request, the next 48 (external) clock cycles are used to prioritize the interrupt, and push the two PC bytes and the FLAG register onto the stack. The following nine cycles are used to fetch the interrupt vector from external memory. The first byte of the interrupt service routine is fetched beginning on the 58th TpC cycle following the internal sample point, which corresponds to the 63rd TpC cycle following the external interrupt sample point. IRQ0 - IRQ5 IRQ IMR 6 Global Interrupt Enable IPR Interrupt Request PRIORITY LOGIC Vector Select Figure 23. Interrupt Block Diagram 25 Z86C61/62/96 Z8(R) MICROCONTROLLER FUNCTIONAL DESCRIPTION (Continued) Clock. The Z86C61/62/96 on-chip oscillator has a highgain, parallel-resonant amplifier for connection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal should be AT cut, 1 MHz to 20 MHz max, and series resistance (RS) is less than or equal to 100 Ohms. The crystal should be connected across XTAL1 and XTAL2 using the recommended capacitors (10 pF < CL < 100 pF) from each pin to device ground (Figure 24). Note: Actual capacitor values specified by the crystal manufacturer. XTAL1 C1 C1 L XTAL2 C2 C2 XTAL1 XTAL1 XTAL2 XTAL2 Ceramic Resonator or Crystal LC Clock External Clock Figure 24. Oscillator Configuration HALT. Turns off the internal CPU clock but not the XTAL oscillation. The counter/timers and the external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 5 A (typical) or less. The STOP mode is terminated by a reset, which causes the processor to restart the application program at address 000CH. In order to enter STOP (or HALT) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a NOP (opcode=0FFH) immediately before the appropriate sleep instruction, i.e., FF 6F FF 7F NOP STOP NOP HALT ; clear the pipeline ; enter STOP mode or ; clear the pipeline ; enter HALT mode 26 Z86C61/62/96 Z8(R) MICROCONTROLLER ABSOLUTE MAXIMUM RATINGS Symbol VCC TSTG TA Description Min Max +7.0 +150 Units V C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Supply Voltage* -0.3 Storage Temp -65 Oper Ambient Temp Notes: * Voltages on all pins with respect to GND. See ordering information STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 25). From Output Under T est I 150 pF Figure 25. Test Load Diagram 27 Z86C61/62/96 Z8(R) MICROCONTROLLER DC ELECTRICAL CHARACTERISTICS Z86C61/62/96 TA = 0C to +70C Min Max 0.85 VCC VSS - 0.3 2 VSS - 0.3 2.4 7 VCC + 0.3 0.8 VCC + 0.3 0.2 VCC TA = -40C to +105C Min Max 0.85 VCC VSS - 0.3 2 VSS - 0.3 2.4 7 VCC + 0.3 0.8 VCC + 0.3 0.2 VCC VCC - 100 mV 0.4 0.6 VCC + 0.3 0.2 VCC 2 2 -80 35 40 15 20 20 24 30 4.5 5 5 Sym Parameter VCH VCL VIH VIL VOH VOH VOL VOL VRH VRl IIL IOL IIR ICC ICC ICC1 ICC2 IALL Max Input Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Output Low Voltage Reset Input High Voltage Reset Input Low Voltage Input Leakage Output Leakage Reset Input Current Supply Current Supply Current Standby Current Standby Current Auto Latch Low Current Typical @ 25C Units V V V V V V V V V V V A A A mA mA mA A A Conditions IIN < 250 A Driven by External Clock Generator Driven by External Clock Generator IOH = -2.0 mA IOH = -100 A IOL = +5.0 mA [3] IOL = +4.0 mA [2] VCC - 100 mV 0.4 0.6 0.85 VCC VCC + 0.3 -0.3 -2 -2 0.2 VCC 2 2 -80 35 40 15 10 14 0.85 VCC -0.3 -2 -2 VIN = 0 V, VCC VIN = 0 V, VCC VRL = 0 V [1] @ 16 MHz [1] @ 20 MHz [1] HALT Mode VIN = 0 V, VCC @ 16 MHz [1] STOP Mode VIN = 0 V, VCC -14 -20 Notes: [1] All inputs driven to either 0V or VCC, outputs floating. [2] VCC = 3.0V to 3.6V [3] VCC = 4.5V to 5.5V 28 Z86C61/62/96 Z8(R) MICROCONTROLLER AC CHARACTERISTICS R//W 13 12 Port 0, /DM 16 18 3 Port 1 1 A7 - A0 2 D7 - D0 IN 9 /AS 8 4 5 6 11 /DS (Read) 17 10 Port 1 A7 - A0 14 D7 - D0 OUT 15 7 /DS (Write) 17 Figure 26. External I/O or Memory Read/Write 29 Z86C61/62/96 Z8(R) MICROCONTROLLER AC CHARACTERISTICS External I/O or Memory Read and Write Timing Z86C61/62/96 (16 MHz) TA = 0C to +70C 16 MHz Min Max 25 35 150 40 0 135 80 75 0 50 35 25 35 25 35 210 45 25 45 25 80 75 0 50 35 25 35 25 35 210 40 0 135 TA = -40C to +105C 16 MHz Min Max 25 35 150 No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) Parameter Address Valid to /AS rise Delay /AS rise to Address Float Delay /AS rise to Read Data Req'd Valid /AS Low Width Address Float to /DS fall /DS (Read) Low Width /DS (Write) Low Width /DS fall to Read Data Req'd Valid Read Data to /DS rise Hold Time /DS rise to Address Active Delay /DS rise to /AS fall Delay R//W Valid to /AS rise Delay /DS rise to R//W Not Valid Write Data Valid to /DS fall (Write) Delay /DS rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid /AS rise to /DS fall Delay /DM Valid to /AS rise Delay Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [1,2,3] [1,2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [1,2,3] [2,3] [2,3] Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. Standard Test Load All timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0. Clock Dependent Formulas Number 1 2 3 4 6 7 8 10 11 12 13 14 15 16 17 18 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TwDSR TwDSW TdDSR(DR) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) Equation 0.40 TpC + 0.32 0.59 TpC - 3.25 2.83 TpC + 6.14 0.66 TpC - 1.65 2.33 TpC - 10.56 1.27 TpC + 1.67 1.97 TpC - 42.5 0.8 TpC 0.59 TpC - 3.14 0.4 TpC 0.8 TpC - 15 0.4 TpC 0.88 TpC - 19 4 TpC - 20 0.91 TpC - 10.7 0.9 TpC - 26.3 30 Z86C61/62/96 Z8(R) MICROCONTROLLER AC CHARACTERISTICS External I/O or Memory Read and Write Timing Z86C61/62/96 (20 MHz) TA = 0C to +70C 20 MHz Min Max 15 25 120 30 0 105 65 55 0 40 25 20 25 20 25 150 35 15 35 15 65 55 0 40 25 20 25 20 25 150 30 0 105 TA = -40C to +105C 20 MHz Min Max 25 35 120 No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) Parameter Address Valid to /AS rise Delay /AS rise to Address Float Delay /AS rise to Read Data Req'd Valid /AS Low Width Address Float to /DS fall /DS (Read) Low Width /DS (Write) Low Width /DS fall to Read Data Req'd Valid Read Data to /DS rise Hold Time /DS rise to Address Active Delay /DS rise to /AS fall Delay R//W Valid to /AS rise Delay /DS rise to R//W Not Valid Write Data Valid to /DS fall (Write) Delay /DS rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid /AS rise to /DS fall Delay /DM Valid to /AS rise Delay Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [1,2,3] [1,2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [1,2,3] [2,3] [2,3] Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. 31 Z86C61/62/96 Z8(R) MICROCONTROLLER AC CHARACTERISTICS Additional Timing Diagram 1 3 Clock 2 7 7 2 3 TIN 4 6 5 IRQN 8 9 Figure 27. Additional Timing AC CHARACTERISTICS Additional Timing Table Z86C61/62/96 TA = 0C to +70C 20/16 MHz Min Max 50/62.5 1000 10 25 75 5 TpC 8 TpC 100 70 5 TpC 5 TpC TA = -40C to +105C 20/16 MHz Min Max 50/62.5 1000 10 25 75 5 TpC 8 TpC 100 50 5 TpC 5 TpC No 1 2 3 4 5 6 7 8a 8b 9 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH Parameter Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Times Interrupt Request Input Low Times Interrupt Request Input Low Times Interrupt Request Input High Times Units ns ns ns ns ns ns ns ns ns ns Notes [1] [1] [1] [2] [2] [2] [2] [2,4] [2,5] [2,3] Notes: [1] Clock timing references use 0.8Vcc for a logic 1 and 0.8V for a logic 0. [2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. [3] Interrupt references request through Port 3. [4] Interrupt request through Port 3 (P33-P31). [5] Interrupt request through Port 30. 32 Z86C61/62/96 Z8(R) MICROCONTROLLER AC CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid Next Data In Valid 1 3 2 /DAV (Input) 4 Delayed DAV 5 6 RDY (Output) Delayed RDY Figure 28. Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 /DAV (Output) 8 10 9 Delayed DAV 11 RDY (Input) Delayed RDY Figure 29. Output Handshake Timing AC ELECTRICAL CHARACTERISTICS Handshake Timing Table Z86C61/62/96 TA = 0C to +70C 20/16 MHz Min Max 0 145 110 115 115 0 TpC 0 115 110 115 TA = -40C to +105C 20/16 MHz Min Max 0 145 110 115 115 0 TpC 0 115 110 115 No 1 2 3 4 5 6 7 8 9 10 11 Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdRDY0(DAV) TdDO(DAV) TdDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV) Parameter Data In Setup Time Data In Hold Time Data Available Width DAV fall to RDY fall Delay DAV rise to RDY rise Delay RDY rise to DAV fall Delay Data Out to DAV fall Delay DAV fall to RDY fall Delay RDY fall to DAV rise Delay RDY Width RDY rise to DAV fall Delay Data Direction IN IN IN IN IN IN OUT OUT OUT OUT OUT 33 Z86C61/62/96 Z8(R) MICROCONTROLLER Z8 CONTROL REGISTER DIAGRAMS R240 SIO D7 D6 D5 D4 D3 D2 D1 D0 R243 PRE1 D7 D6 D5 D4 D3 D2 D1 D0 Serial Data (D0 = LSB) Count Mode 0 T1 Single Pass 1 T1 Modulo N Clock Source 1 T1 Internal 0 T1 External Timing Input (TIN) Mode Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) Figure 30. Serial I/O Register (F0H: Read/Write) R241 TMR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 No Function Load T0 Disable T0 Count Enable T0 Count No Function Load T1 Disable T1 Count Enable T1 Count R244 T0 Figure 33. Prescaler 1 Register (F3H: Write Only) D7 D6 D5 D4 D3 D2 D1 D0 TIN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) TOUT Modes 00 Not Used 01 T0 Out 10 T1 Out 11 Internal Clock Out R245 PRE0 T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T0 Current Value (When Read) Figure 34. Counter/Timer 0 Register (F4H: Read/Write) Figure 31. Timer Mode Register (F1H: Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Count Mode 0 T0 Single Pass 1 T0 Modulo N R242 T1 D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) T1 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T1 Current Value (When Read) Figure 35. Prescaler 0 Register (F5H: Write Only) Figure 32. Counter/Timer 1 Register (F2H: Read/Write) 34 Z86C61/62/96 Z8(R) MICROCONTROLLER R246 P2M D7 D6 D5 D4 D3 D2 D1 D0 R248 P01M D7 D6 D5 D4 D3 D2 D1 D0 P20 - P27 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input P00 - P00 Mode 00 Output 01 Input 1X A11 - A8 Stack Selection 0 External 1 Internal P17 - P10 Mode 00 Byte Output 01 Byte Input 10 AD7 - AD0 11 High-Impedance AD7 - DA0, /AS, /DS, /R//W, A11 - A8, A15 - A12, If Selected Reserved (Must be 0) Figure 36. Port 2 Mode Register (F6H: Write Only) R247 P3M D7 D6 D5 D4 D3 D2 D1 D0 0 Port 2 Open Drain 1 Port 2 Push-pull Reserved (Must be 0) 0 P32 = Input P35 = Output 1 P32 = /DAV0/RDY0 P35 = RDY0//DAV0 00 01 10 11 P33 = Input P34 = Output P33 = Input P34 = /DM P33 = /DAV1/RDY1 P34 = RDY1//DAV1 P07 - P04 Mode 00 Output 01 Input 1X A 15 - A12 Figure 38. Port 0 and 1 Mode Register (F8H: Write Only) R249 IPR D7 D6 D5 D4 D3 D2 D1 D0 0 P31 = Input (TIN) P36 = Output (TOUT) 1 P31 = /DAV2/RDY2 P36 = RDY2//DAV2 0 1 P30 = Input P37 = Output P30 = Serial In P37 = Serial Out 0 Parity Off 1 Parity On Interrupt Group Priority Reserved = 000 C > A > B = 001 A > B > C = 010 A > C > B = 011 B > C > A = 100 C > B > A = 101 B > A > C = 110 Reserved = 111 IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0) Figure 37. Port 3 Mode Register (F7H: Write Only) Figure 39. Interrupt Priority Register (F9H: Write Only) 35 Z86C61/62/96 Z8(R) MICROCONTROLLER Z8 CONTROL REGISTER DIAGRAMS (Continued) R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0 IRQ0 = P32 IRQ1 = P33 IRQ2 = P31 IRQ3 = P30 IRQ4 = T0 IRQ5 = T1 Input (D0 = IRQ0) Input Input Input, Serial Input Serial Output R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register Pointer Working Register Pointer Reserved (Must be 0) Figure 43. Register Pointer Register (FDH: Read/Write) Figure 40. Interrupt Request Register (FAH: Read/Write) R254 SPH D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer Upper Byte (SP15 - SP8) R251 IMR D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 Enables IRQ5-IRQ0 (D0 = IRQ0) Enables RAM Protect Enables Interrupts Figure 44. Stack Pointer Register (FEH: Read/Write) R255 SPL D7 D6 D5 D4 D3 D2 D1 D0 Figure 41. Interrupt Mask Register (FBH: Read/Write) Stack Pointer Lower Byte (SP7 - SP0) R252 FLAGS D7 D6 D5 D4 D3 D2 D1 D0 Figure 45. Stack Pointer Register (FFH: Read/Write) User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Figure 42. Flag Register (FCH: Read/Write) 36 Z86C61/62/96 Z8(R) MICROCONTROLLER Z8 EXPANDED REGISTER FILE CONTROL REGISTERS P4 (FH) 02H D7 D6 D5 D4 D3 D2 D1 D0 P45M (FH) 06H D4 D0 0 Port 4 Open-drain* 1 Port 4 Push-pull Reserved (Must be 0) 0 Port 5 Open-drain* 1 Port 5 Push-pull Reserved (Must be 0) *Default Value After RESET Data 0 Defines Level 0 1 Defines Level 1 Figure 46. Port 4 Data Register (F)02: (Read/Write) P4M (FH) 03H D7 D6 D5 D4 D3 D2 D1 D0 Figure 50. Port 4/5 Mode Register (F)06: (Write Only) P40 - P47 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input P6 (FH) 07H D7 D6 D5 D4 D3 D2 D1 D0 Figure 47. Port 4 Direction Register (F)03: (Write Only) Data 0 Defines Level 0 1 Defines Level 1 Reserved (Must be 0) P5 (FH) 04H D7 D6 D5 D4 D3 D2 D1 D0 Figure 51. Port 6 Data Register (F)07: (Read/Write) Data 0 Defines Level 0 1 Defines Level 1 P6D (FH) 08H D3 D2 D1 D0 Figure 48. Port 5 Data Register (F)04: (Read/Write) P60 - P63 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input* Reserved (Must be 0) P5D (FH) 05H *Default Value After RESET D7 D6 D5 D4 D3 D2 D1 D0 *Default Value After RESET P50 - P57 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input* Figure 52. Port 6 Direction Register (F)08: (Write Only) P6M (FH) 09H Figure 49. Port 5 Direction Register (F)05: (Write Only) D7 D6 D5 D4 D3 D2 D1 D0 0 1 *Default Value After RESET Port 6 Open-drain* Port 6 Push-pull Figure 53. Port 6 Mode Register (F)09: (Write Only) 37 Z86C61/62/96 Z8(R) MICROCONTROLLER INSTRUCTION SET NOTATION Addressing Modes. The following notation is used to describe the addressing modes and instruction operations as shown in the instruction summary. Symbol IRR Irr X DA RA IM R r IR Ir RR Meaning Indirect register pair or indirect workingregister pair address Indirect working-register pair only Indexed address Direct address Relative address Immediate Register or working-register address Working-register address only Indirect-register or indirect working-register address Indirect working-register address only Register pair or working register pair address Flags. Control register (R252) contains the following six flags: Symbol C Z S V D H Meaning Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Affected flags are indicated by: 0 1 * x Clear to zero Set to one Set to clear according to operation Unaffected Undefined Symbols. The following symbols are used in describing the instruction set. Symbol dst src cc @ SP PC FLAGS RP IMR Meaning Destination location or contents Source location or contents Condition code Indirect address prefix Stack Pointer Program Counter Flag register (Control Register 252) Register Pointer (R253) Interrupt mask register (R251) 38 Z86C61/62/96 Z8(R) MICROCONTROLLER CONDITION CODES Value 1000 0111 1111 0110 1110 1101 0101 0100 1100 0110 1110 1001 0001 1010 0010 1111 0111 1011 0011 0000 Mnemonic C NC Z NZ PL MI OV NOV EQ NE GE LT GT LE UGE ULT UGT ULE F Meaning Always True Carry No Carry Zero Not Zero Plus Minus Overflow No Overflow Equal Not Equal Greater Than or Equal Less than Greater Than Less Than or Equal Unsigned Greater Than or Equal Unsigned Less Than Unsigned Greater Than Unsigned Less Than or Equal Never True (Always False) Flags Set C=1 C=0 Z=1 Z=0 S=0 S=1 V=1 V=0 Z=1 Z=0 (S XOR V) = 0 (S XOR V) = 1 [Z OR (S XOR V)] = 0 [Z OR (S XOR V)] = 1 C=0 C=1 (C = 0 AND Z = 0) = 1 (C OR Z) = 1 39 Z86C61/62/96 Z8(R) MICROCONTROLLER INSTRUCTION FORMATS OPC CCF, DI, EI, IRET, NOP, RCF, RET, SCF OPC dst One-Byte Instructions OPC MODE OR 1110 dst/src dst/src CLR, CPL, DA, DEC, DECW, INC, INCW, POP, PUSH, RL, RLC, RR, RRC, SRA, SWAP JP, CALL (Indirect) OPC src dst MODE OR OR 1110 1110 src dst ADC, ADD, AND, CP, LD, OR, SBC, SUB, TCM, TM, XOR OPC dst OR 1110 dst OPC dst MODE OR 1110 dst ADC, ADD, AND, CP, LD, OR, SBC, SUB, TCM, TM, XOR OPC VALUE SRP VALUE MODE OPC dst MODE src ADC, ADD, AND, CP, OR, SBC, SUB, TCM, TM, XOR LD, LDE, LDEI, LDC, LDCI MODE dst/src src dst OPC OR OR 1110 1110 src dst LD MODE dst/src OPC src/dst OPC x LD ADDRESS dst/src OPC OR 1110 src LD cc DAU dst OPC LD DAL OPC JP src/dst VALUE OPC dst/CC RA OPC DJNZ, JR DAU DAL CALL FFH 6FH 7FH STOP/HALT Two-Byte Instructions Three-Byte Instructions INSTRUCTION SUMMARY Note: Assignment of a value is indicated by the symbol " ". For example: dst dst + src indicates that the source data is added to the destination data and the result is stored in the destination location. The notation "addr (n)" is used to refer to bit (n) of a given operand location. For example: dst (7) refers to bit 7 of the destination operand. 40 Z86C61/62/96 Z8(R) MICROCONTROLLER INSTRUCTION SUMMARY (Continued) Instruction and Operation Address Mode Opcode Flags Affected dst src Byte (Hex) C Z S V D H 1[ ] TTTT0T Instruction and Operation INC dst dstdst + 1 Address Mode Opcode Flags Affected dst src Byte (Hex) C Z S V D H r R IR INCW dst dstdst + 1 IRET FLAGS@SP; SPSP +1 PC@SP; SPSP + 2; IMR(7)1 JP cc, dst if cc is true PCdst JR cc, dst if cc is true, PCPC +dst Range: +127, -128 LD dst, src dstsrc DA IRR RA RR IR rE r=0-F 20 21 A0 A1 BF TTT- ADC dst, src dstdst +src + C ADD dst, src dstdst +src AND dst, src dstdst AND src CALL dst SPSP - 2 @SPPC, PCdst CCF CNOT C CLR dst dst0 COM dst dstNOT dst CP dst, src dst - src DA dst dstDA dst DEC dst dstdst - 1 DECW dst dstdst - 1 DI IMR(7)0 DJNZr, dst rr - 1 if r 0 PCPC +dst Range: +127, -128 EI IMR(7)1 HALT RA R IR R IR 0[ ] TTTT0T - TTT- - 5[ ] - TT0- - TTTTTT DA IRR D6 D4 - - - - - - EF T- - - - cD c=0-F 30 cB c=0-F - B0 B1 60 61 A[ ] - - - - - - - - - - - - - TT0- - TTTT- - R IR R IR RR IR 40 41 00 01 80 81 8F TTTX- - r r R r X r Ir R R R IR IR Im R r X r Ir r R IR IM IM R Irr Irr - TTT- - - TTT- - - - - - - - rC r8 r9 r=0-F C7 D7 E3 F3 E4 E5 E6 E7 F5 C2 C3 - - - - - - rA r=0-F - - - - - LDC dst, src LDCI dst, src dstsrc rr +1; rrrr +1 r Ir - 9F - - - - - - 7F - - - - - - 41 Z86C61/62/96 Z8(R) MICROCONTROLLER INSTRUCTION SUMMARY (Continued) Instruction and Operation NOP OR dst, src dstdst OR src POP dst dst@SP; SPSP + 1 PUSH src SPSP - 1; @SPsrc RCF C0 RET PC@SP; SPSP + 2 RL dst C 7 0 Address Mode Opcode Flags Affected dst src Byte (Hex) C Z S V D H FF 4[ ] - Instruction and Operation STOP SUB dst, src dstdstsrc SWAP dst 7 4 3 0 Address Mode Opcode Flags Affected dst src Byte (Hex) C Z S V D H 6F 2[ ] - TT0- TTTT1T R IR 50 51 - - - - - - R IR F0 F1 XTTX- - R IR 70 71 - - - - - TCM dst, src (NOT dst) AND src 6[ ] TT0- CF 0- - - - TM dst, src dst AND src 7[ ] TT0- AF - - - - - XOR dst, src dstdst XOR src B[ ] TT0- R IR 90 91 TTTT- These instructions have an identical set of addressing modes, which are encoded for brevity. The first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically by a `[ ]' in this table, and its value is found in the following table to the left of the applicable addressing mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13. RLC dst C 7 0 R IR 10 11 TTTT- - RR dst C 7 0 R IR E0 E1 TTTT- - RRC dst C 7 0 R IR C0 C1 3[ ] TTTT- - Address Mode dst src r r Ir R IR IM IM Lower Opcode Nibble [2] [3] [4] [5] [6] [7] SBC dst, src dstdstsrcC SCF C1 SRA dst C 7 0 TTTT1T r R R DF 1- - - - - R IR D0 D1 TTT0- - R IR SRP src RPsrc Im 31 - - - - - - 42 Z86C61/62/96 Z8(R) MICROCONTROLLER OPCODE MAP Lower Nibble (Hex) 0 0 6.5 DEC R1 6.5 RLC R1 6.5 INC R1 8.0 JP IRR1 8.5 DA R1 10.5 POP R1 6.5 COM R1 10/12.1 PUSH R2 10.5 DECW RR1 6.5 RL R1 10.5 INCW RR1 6.5 CLR R1 6.5 RRC R1 6.5 SRA R1 6.5 RR R1 8.5 SWAP R1 1 6.5 DEC IR1 6.5 RLC IR1 6.5 INC IR1 6.1 SRP IM 8.5 DA IR1 10.5 POP IR1 6.5 COM IR1 12/14.1 PUSH IR2 10.5 DECW IR1 6.5 RL IR1 10.5 INCW IR1 6.5 CLR IR1 6.5 RRC IR1 6.5 SRA IR1 6.5 RR IR1 8.5 SWAP IR1 2 2 6.5 ADD r1, r2 6.5 ADC r1, r2 6.5 SUB r1, r2 6.5 SBC r1, r2 6.5 OR r1, r2 6.5 AND r1, r2 6.5 TCM r1, r2 6.5 TM r1, r2 12.0 LDE r1, Irr2 12.0 LDE r2, Irr1 6.5 CP r1, r2 6.5 XOR r1, r2 12.0 LDC r1, Irr2 12.0 LDC r1, Irr2 3 6.5 ADD r1, Ir2 6.5 ADC r1, Ir2 6.5 SUB r1, Ir2 6.5 SBC r1, Ir2 6.5 OR r1, Ir2 6.5 AND r1, Ir2 6.5 TCM r1, Ir2 6.5 TM r1, Ir2 18.0 LDEI Ir1, Irr2 18.0 LDEI Ir2, Irr1 6.5 CP r1, Ir2 6.5 XOR r1, Ir2 18.0 LDCI Ir1, Irr2 18.0 LDCI Ir1, Irr2 6.5 LD r1, IR2 6.5 LD Ir1, r2 4 10.5 ADD R2, R1 10.5 ADC R2, R1 10.5 SUB R2, R1 10.5 SBC R2, R1 10.5 OR R2, R1 10.5 AND R2, R1 10.5 TCM R2, R1 10.5 TM R2, R1 5 10.5 ADD IR2, R1 10.5 ADC IR2, R1 10.5 SUB IR2, R1 10.5 SBC IR2, R1 10.5 OR IR2, R1 10.5 AND IR2, R1 10.5 TCM IR2, R1 10.5 TM IR2, R1 6 10.5 ADD R1, IM 10.5 ADC R1, IM 10.5 SUB R1, IM 10.5 SBC R1, IM 10.5 OR R1, IM 10.5 AND R1, IM 10.5 TCM R1, IM 10.5 TM R1, IM 7 8 9 A B C D 12.10.0 JP cc, DA E 6.5 INC r1 F 1 2 3 4 5 6 Upper Nibble (Hex) 7 6.5 10.5 LD ADD IR1, IM r1, R2 10.5 ADC IR1, IM 10.5 SUB IR1, IM 10.5 SBC IR1, IM 10.5 OR IR1, IM 10.5 AND IR1, IM 10.5 TCM IR1, IM 10.5 TM IR1, IM 12/10.5 12/10.0 6.5 6.5 LD JR DJNZ LD r2, R1 r1, RA cc, RA r1, IM 6.0 STOP 7.0 HALT 6.1 DI 6.1 EI 8 9 A B C D E F 10.5 10.5 10.5 10.5 CP CP CP CP R2, R1 IR2, R1 R1, IM IR1, IM 10.5 10.5 10.5 10.5 XOR XOR XOR XOR R2, R1 IR2, R1 R1, IM IR1, IM 10.5 LD r1,x,R2 10.5 20.0 20.0 LD CALL CALL* r2,x,R1 DA IRR1 10.5 10.5 10.5 10.5 LD LD LD LD R2, R1 IR2, R1 R1, IM IR1, IM 10.5 LD R2, IR1 3 2 3 1 14.0 RET 16.0 IRET 6.5 RCF 6.5 SCF 6.5 CCF 6.0 NOP Bytes per Instruction Lower Opcode Nibble Pipeline Cycles 4 Execution Cycles Upper Opcode Nibble Legend: R = 8-bit Address r = 4-bit Address R1 or r1 = Dst Address R2 or r2 = Src Address Sequence: Opcode, First Operand, Second Operand Note: Blank areas not defined. *2-byte instruction appears as a 3-byte instruction A 10.5 CP R1 , R 2 Mnemonic First Operand Second Operand 43 Z86C61/62/96 Z8(R) MICROCONTROLLER PACKAGE INFORMATION 40-Pin Plastic DIP Package 44-Pin PLCC Package 44 Z86C61/62/96 Z8(R) MICROCONTROLLER 64-Pin Plastic DIP Package 68-Pin PLCC Package 45 Z86C61/62/96 Z8(R) MICROCONTROLLER ORDERING INFORMATION Z86C61/62/96 16 MHz 40-pin DIP Z86C6116PSC 16 MHz 64-pin DIP Z86C6216PSC 20 MHz 64-pin DIP Z86C9620PSC 44-pin PLCC Z86C6116VSC 44-pin QFP 286C6116FSC 68-pin PLCC Z86C6216VSC 68-pin PLCC Z86C9620VSC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. CODES Package P = Plastic DIP V = Plastic Chip Carrier Preferred Temperature S = 0C to +70C Longer Lead Time E = -40C to +105C Speeds 16 = 16 MHz 20 = 20 MHz Environmental C = Plastic Standard Example: Z 86C61 16 P S C is an 86C61, 16 MHz, DIP 0C to +70C, Plastic Standard Flow , Environmental Flow T emperature Package Speed Product Number Zilog Prefix 46 |
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